DN_Readbacker
Realtime FPGA Readback for design visibility and debug. Display multiple register
captures of the entire design in a waveform viewer, with or without stopping the
system clock.
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PCIe PIPE Slowdown Core
Slows a PCIe GEN1/GEN2 PIPE interface to 31MHz, dramatically easing the task of
FPGA-based PCIe prototyping. Read More...
PIN Multiplexing
The Dinigroup LVDS IO Pin Multiplexing design dramatically increases the available
interconnect between FPGA's while running at the highest possible data rates.
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