AV150 Virtex UltraScale+

Overview

The AV150 is a 3U OpenVPX data conversion and processing board with four 14-bit 3 Gsps ADCs and four 16-bit 6 Gsps DACs (12 Gsps update rate). Processing is done on an AMD Virtex UltraScale+ VU7P, VU9P or VU13P FPGA with two DDR4 banks. It comes air cooled or conduction cooled for phased-array radar, electronic warfare, MIMO and wideband communication.

Built for

Phased-array radar transmit and receive
Electronic warfare (ESM/ECM)
MIMO systems
Wideband communication

Key features

Choice of FPGA

Virtex UltraScale+ VU7P, VU9P or VU13P lets the processing power match the application.

ADC with DDC

Four 14-bit 3 Gsps ADCs each have two digital down converters with 2 to 48 decimation.

DAC with DUC

Four 16-bit DACs run at 6 Gsps, with digital up converters and 2x to 24x interpolation.

Flexible clocking

The internal low jitter synthesiser can be replaced by an external clock or reference.

OpenVPX interface

PCIe, Gigabit Ethernet, Aurora and many user-defined I/O run over the VPX backplane.

Development support

Windows and Linux drivers, VHDL cores and a Vivado base design are supplied.

Specifications

FPGA: AMD Virtex UltraScale+ XCVU7P, XCVU9P or XCVU13P, speed grade -2, industrial
ADC: 4 channels, 14-bit, up to 3 Gsps
DAC: 4 channels, 16-bit, up to 6 Gsps (12 Gsps update rate)
DDC / DUC: 2 DDC per ADC (decimation 2 to 48), 1 DUC per DAC (interpolation 2x to 24x), 48-bit NCO
Analogue I/O: Input 10 MHz to 8 GHz, output 10 MHz to 7.5 GHz, SMPM, 50 Ohm
Clock: Internal 2 to 6 GHz synthesiser, external clock or reference 10 to 100 MHz
Memory: 2 banks 1G64 DDR4-2666 SDRAM, 2 Gbit QSPI flash
VPX P1: Two data plane fat pipes, one expansion fat pipe, ultra-thin control pipes
VPX P2: USB 2.0, USB to UART, 24 LVDS pairs (48 LVCMOS)
Form factor: 3U OpenVPX, air or conduction cooled
Operating temp: 0 to 55 C (air, EAC4), -40 to 70 C (conduction, ECC3)
Software: Windows 10 and Linux 64-bit drivers, Vivado 2022.2
Export class: ECCN 3A002h1